FIG. 1 illustrates a cross sectional view of a conventional multi-stack chip size package (CSP).
Referring to FIG. 1, a first chip (or die) 20 is adhered on a substrate 10, e.g., a printed circuit board, with an epoxy and a second chip (or die) 30 is stacked thereon with the epoxy. Bonding pads on the first and the second chip 20 and 30 are electrically connected with terminals on the printed circuit board 10 by conductive wires 50. A resin, e.g., an epoxy molding compound (EMC) 40 is used to mold the first and the second chip 20 and 30, and the electrical connection between the whole package and an another printed circuit board can be achieved by ball grid array using solder balls 60.
The drawback of the conventional multi-stack chip size packaged device is that a thickness thereof is to be enlarged, e.g., about 1.4 mm, because of the molding material of the multi-stack CSP, i.e., the resin, to thereby require a long conductive wire 50, i.e., a long signal transmission path. Therefore, the characteristics of the multi-stack chip size packaged device are deteriorated and the applicability thereof is also reduced. In addition, heat dissipation thereof is not effective.